module beamforming_top (
    input  wire        clk_50m,
    input  wire        rst_n,
    input  wire [15:0] i2s_sdata,
    output wire        i2s_bclk,
    output wire        i2s_lrclk,
    output wire        i2s_tx_data,
    output wire        i2s_tx_vld,
    
    // 控制和监控接口
    input  wire [1:0]  mode_select,
    output wire [7:0]  status_led,
    output wire [31:0] debug_output
);

// 模块互联信号定义
wire [23:0] mic_data [15:0];
wire        data_vld [15:0];
wire        frame_sync;

wire [23:0] synced_data [15:0];
wire        data_ready;

wire [23:0] time_domain [15:0];
wire        time_vld;
wire [31:0] freq_real [15:0][127:0];
wire [31:0] freq_imag [15:0][127:0];
wire        freq_vld;

wire [8:0]  target_angle;
wire [7:0]  angle_confidence;
wire        doa_vld;

wire [23:0] beamformed;
wire        beam_vld;

wire [23:0] final_output;
wire        output_vld;

// 模块实例化
i2s_receiver_array u_i2s_array (...);
data_synchronizer u_sync (...);
preprocessor u_pre (...);
doa_estimator u_doa (...);
beamforming_processor u_beam (...);
post_processor u_post (...);
system_controller u_ctrl (...);

endmodule